1. Field of the Invention
The present invention relates to a method of fabricating a transistor having a Schottky barrier, and more particularly, to a method of fabricating a transistor having a Schottky barrier that includes a three dimensional gate formed on a fin type channel.
2. Description of the Related Art
Studies have been conducted to scale down a metal oxide semiconductor field effect transistor (MOSFET) which is a unit device of a highly integrated logic circuit in order to increase performance and integration density. As the scale down of the MOSFET is progressed, a distance between source and drain is reduced, and thus, a short channel effect (SCE), that is, a phenomenon that a drain field modulates a gate field to be applied to a channel occurs resulting in the reduction of channel controllability of the gate. This phenomenon causes an electrical characteristic such as punch-through, drain-induced barrier lowering (DIBL), or threshold voltage roll-off.
The SCE severely occurs in a transistor having a very short gate length, for example, 50 nm or less, and as a result, a switching function which is the basic function of the transistor may be damaged. In order to address this problem, a channel doping method, an ultra-shallow junction method, or a gate dielectric thinning method may be used. However, these methods have a limit due to attendant problems such as a random doping problem and a gate leakage.
As a method of addressing the scale down problem, a transistor that has an increased contact surface between the channel and the gate by forming a three dimensional gate and has low power consumption by forming a Schottky barrier between a source and drain, and the channel.
Meanwhile, when a scale down transistor is fabricated, aligning errors between a channel and a source and a drain may occur during the formation of the source and drain are formed after forming the channel due to a plurality of mask processes.